A 10 GHz 4: 1 MUX and 1: 4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC

This paper describes the implementation of a scalable SiGe FPGA that serves as an interleaving and deinterleaving block in a high-speed reconfigurable data acquisition system. In this paper, the different generations of SiGe configurable blocks (Basic Cells(BC)) evolved from the Xilinx 6200 are presented and measured. The latest generation has a 94% reduction in power consumption (from 71 to 4.2mW) and an 82.5% reduction of the propagation delay (from 238 to 42 ps) compared to the first generation design. To demonstrate the SiGe FPGA’s capabilities of handling gigahertz signals, the SiGe FPGAs configured as the 4:1 multiplexer and 1:4 demultiplexer were designed to run at 10Gbps. The comparisons between the SiGe and CMOS FPGAs are also provided. With these design results, the SiGe FPGA is able to process gigahertz signals such as S and K microwave bands. r 2004 Elsevier B.V. All rights reserved.